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? 2011 microchip technology inc. ds25007a-page 1 mcp6v27 features ? high dc precision: -v os drift: 50 nv/c (maximum) -v os : 2 v (maximum) -a ol : 125 db (minimum) - psrr: 125 db (minimum) - cmrr: 120 db (minimum) -e ni : 1.0 v p-p (typical), f = 0.1 hz to 10 hz -e ni : 0.32 v p-p (typical), f = 0.01 hz to 1 hz ? low power and supply voltages: -i q : 620 a/amplifier (typical) - wide supply voltage range: 2.3v to 5.5v ?easy to use: - rail-to-rail input/output - gain bandwidth product: 2 mhz (typical) - unity gain stable - available in dual ? extended temperature range: -40c to +125c typical applications ? portable instrumentation ? sensor conditioning ? temperature measurement ? dc offset correction ? medical instrumentation design aids ? spice macro models ?filterlab ? software ? microchip advanced part selector (maps) ? analog demonstration and evaluation boards ? application notes related parts parts with lower power, lower bandwidth and higher noise: ? mcp6v01/2/3: spread clock ? mcp6v06/7/8: non-spread clock description the microchip technology inc. mcp6v27 dual operational amplifier has input offset voltage correction for very low offset and offset drift. this device has a wide gain bandwidth product (2 mhz, typical) and strongly rejects switching noise. it is unity gain stable, has no 1/f noise, and has good psrr and cmrr. this product operates with a single supply voltage as low as 2.3v, while drawing 620 a/amplifier (typical) of quiescent current. the microchip technology inc. mcp6v27 op amp is offered as a dual. it is designed in an advanced cmos process. package types (top view) typical application circuit v ina + v ina ? v ss 1 2 3 4 8 7 6 5 v outa v dd v outb v inb ? v inb + mcp6v27 soic, msop * includes exposed thermal pad (ep); see ta b l e 3 - 1 . mcp6v27 4x4 dfn * v ina + v ina ? v ss v outb v inb ? 1 2 3 4 8 7 6 5 v inb + v dd v outa ep 9 offset voltage correction for power driver 10 nf 10 k 10 k 10 k mcp661 v dd /2 500 k v in v out 10 k ? mcp6v27 5k v dd /2 620 a, 2 mhz auto-zeroed op amps
mcp6v27 ds25007a-page 2 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25007a-page 3 mcp6v27 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd ?v ss ..............................................................................6.5v current at input pins ?? ......................................................2 ma analog inputs (v in + and v in ?) ?? .......... v ss ? 1.0v to v dd +1.0v all other inputs and outputs .................. v ss ? 0.3v to v dd +0.3v difference input voltage ............................................. |v dd ?v ss | output short circuit current ....................................... continuous current at output and supply pins ...................................30 ma storage temperature ..........................................-65c to +150c max. junction temperature .............................................. +150c esd protection on all pins (hbm, cdm, mm) 4 kv,1.5 kv, 300v ?notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ?? see section 4.2.1, rail-to-rail inputs . 1.2 specifications table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.3v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2 and r l = 10 k to v l (refer to figure 1-4 and figure 1-5 ). parameters sym min typ max units conditions input offset input offset voltage v os -2 ? +2 v t a = +25c ( note 1 ) input offset voltage drift with temperature (linear temp. co.) tc 1 -50 ? +50 nv/c t a = -40 to +125c ( note 1 ) input offset voltage quadratic temperature coefficient tc 2 ?0.2 ?nv/c 2 t a = -40 to +125c power supply rejection psrr 125 142 ? db ( note 1 ) input bias current and impedance input bias current i b ?+7 ?pa input bias current across temperature i b ?+110 ? pat a = +85c i b ?+1.2 +5 nat a = +125c input offset current i os ?70 ? pa input offset current across temperature i os ?50 ? pat a = +85c i os ?60 ? pat a = +125c common mode input impedance z cm ?10 13 ||12 ? ||pf differential input impedance z diff ?10 13 ||12 ? ||pf note 1: set by design and characterization. due to thermal junction and other effects in the production environment, these parts can only be screened in production (except tc 1 ; see appendix b: ?offset related test screens? ). 2: figure 2-18 shows how v cml and v cmh changed across temperature for the first production lot.
mcp6v27 ds25007a-page 4 ? 2011 microchip technology inc. common mode common-mode input voltage range low v cml ??v ss ? 0.15 v ( note 2 ) common-mode input voltage range high v cmh v dd + 0.2 ? ? v ( note 2 ) common-mode rejection cmrr 120 136 ? db v dd = 2.3v, v cm = -0.15v to 2.5v ( note 1 , note 2 ) cmrr 125 142 ? db v dd = 5.5v, v cm = -0.15v to 5.7v ( note 1 , note 2 ) open-loop gain dc open-loop gain (large signal) a ol 125 147 ? db v dd =2.3v, v out = 0.2v to 2.1v ( note 1 ) a ol 133 155 ? db v dd =5.5v, v out = 0.2v to 5.3v ( note 1 ) output minimum output voltage swing v ol ?v ss +5 v ss + 15 mv g = +2, 0.5v input overdrive maximum output voltage swing v oh v dd ?15 v dd ? 5 ? mv g = +2, 0.5v input overdrive output short circuit current i sc ?12 ? mav dd =2.3v i sc ?22 ? mav dd =5.5v power supply supply voltage v dd 2.3 ? 5.5 v quiescent current per amplifier i q 450 620 800 a i o = 0 por trip voltage v por 1.15 ? 1.65 v table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.3v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2 and r l = 10 k to v l (refer to figure 1-4 and figure 1-5 ). parameters sym min typ max units conditions note 1: set by design and characterization. due to thermal junction and other effects in the production environment, these parts can only be screened in production (except tc 1 ; see appendix b: ?offset related test screens? ). 2: figure 2-18 shows how v cml and v cmh changed across temperature for the first production lot.
? 2011 microchip technology inc. ds25007a-page 5 mcp6v27 table 1-3: temperature specifications table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.3v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l = 10 k to v l and c l = 60 pf (refer to figure 1-4 and figure 1-5 ). parameters sym min typ max units conditions amplifier ac response gain bandwidth product gbwp ? 2.0 ? mhz slew rate sr ? 1.0 ? v/s phase margin pm ? 65 ? g = +1 amplifier noise response input noise voltage e ni ?0.32 ? v p-p f = 0.01 hz to 1 hz e ni ?1.0 ? v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?50 ? nv/ hz f < 5 khz e ni ?29 ? nv/ hz f = 100 khz input noise current density i ni ?0.6 ? fa/ hz amplifier distortion ( note 1 ) intermodulation distortion (ac) imd ? 40 ? v pk v cm tone = 50 mv pk at 1 khz, g n = 1 amplifier step response start up time t str ? 75 ? s g = +1, v os within 50 v of its final value ( note 2 ) offset correction settling time t stl ? 150 ? s g = +1, v in step of 2v, v os within 50 v of its final value output overdrive recovery time t odr ? 45 ? s g = -100, 0.5v input overdrive to v dd /2, v in 50% point to v out 90% point ( note 3 ) note 1: these parameters were characterized using the circuit in figure 1-6 . in figure 2-37 and figure 2-38 , there is an imd tone at dc, a residual tone at 1 khz, other imd tones and clock tones. 2: high gains behave differently; see section 4.3.3, offset at power up . 3: t odr includes some uncertainty due to clock edge timing. electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = +2.3v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c ( note 1 ) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 8l-4x4 dfn ja ?48?c/w ( note 2 ) thermal resistance, 8l-msop ja ?211?c/w thermal resistance, 8l-soic ja ?150?c/w note 1: operation must not cause t j to exceed maximum junction temperature specification (+150c). 2: measured on a standard jc51-7, four layer printed circuit board with ground plane and vias.
mcp6v27 ds25007a-page 6 ? 2011 microchip technology inc. 1.3 timing diagrams figure 1-1: amplifier start up. figure 1-2: offset correction settling time. figure 1-3: output overdrive recovery. 1.4 test circuits the circuits used for the dc and ac tests are shown in figure 1-4 and figure 1-5 . lay the bypass capacitors out as discussed in section 4.3.10, supply bypass- ing and filtering . r n is equal to the parallel combina- tion of r f and r g to minimize bias current effects. figure 1-4: ac and dc test circuit for most non-inverting gain conditions. figure 1-5: ac and dc test circuit for most inverting gain conditions. the circuit in figure 1-6 tests the op amp input?s dynamic behavior (i.e., imd, t str , t stl and t odr ). the potentiometer balances the resistor network (v out should equal v ref at dc). the op amp?s common mode input voltage is v cm =v in /2. the error at the input (v err ) appears at v out with a noise gain of 10 v/v. figure 1-6: test circuit for dynamic input behavior. v dd v os v os +50v v os ?50v t str 0v 2.3v to 5.5v 2.3v v in v os v os +50v v os +50v t stl v in v out v dd v ss t odr t odr v dd /2 v dd r g r f r n v out v in v dd /3 1f c l r l v l 100 nf r iso ? mcp6v27 v dd r g r f r n v out v dd /3 v in 1f c l r l v l 100 nf r iso ? mcp6v27 v dd v out 1f c l r l v l 100 nf r iso 20.0 k 24.9 20.0 k 50 v in v ref 0.1% 0.1% 25 turn 20.0 k 20.0 k 0.1% 0.1% 2.49 k 2.49 k ? mcp6v27
? 2011 microchip technology inc. ds25007a-page 7 mcp6v27 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. 2.1 dc input precision figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage quadratic temperature coefficient. figure 2-4: input offset voltage vs. power supply voltage with v cm =v cml . figure 2-5: input offset voltage vs. power supply voltage with v cm =v cmh . figure 2-6: input offset voltage vs. output voltage. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 5% 10% 15% 20% 25% 30% 35% 40% -2.0 -1.0 0.0 1.0 2.0 input offset voltage (v) percentage of occurrences 20 samples t a = +25c v dd = 2.3v and 5.5v 0% 5% 10% 15% 20% 25% 30% -50 -40 -30 -20 -10 0 10 20 30 40 50 input offset voltage drift; tc 1 (nv/c) percentage of occurrences 20 samples v dd = 2.3v and 5.5 v -5 -4 -3 -2 -1 0 1 2 3 4 5 0.00.51.01.52.02.53.03.54.04.55.05.5 output voltage (v) input offset voltage (v) v dd = 2.3 v v dd = 5.5v representative par t
mcp6v27 ds25007a-page 8 ? 2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. figure 2-7: input offset voltage vs. common mode voltage with v dd =2.3v. figure 2-8: input offset voltage vs. common mode voltage with v dd =5.5v. figure 2-9: cmrr. figure 2-10: psrr. figure 2-11: dc open-loop gain. figure 2-12: cmrr and psrr vs. ambient temperature. -5 -4 -3 -2 -1 0 1 2 3 4 5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input common mode voltage (v) input offset voltage (v) v dd = 2.3v representative part -40c +25c +85c +125c -5 -4 -3 -2 -1 0 1 2 3 4 5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input common mode voltage (v) input offset voltage (v) v dd = 5.5v representative part -40c +25c +85c +125c 0% 5% 10% 15% 20% 25% 30% 35% -0.5 -0.3 0.0 0.3 0.5 1/cmrr (v/v) percentage of occurrences 20 samples t a = +25c v dd = 2.3v v dd = 5.5v 0% 5% 10% 15% 20% 25% 30% -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 1/psrr (v/v) percentage of occurrences 20 samples t a = +25c 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 1/a ol (v/v) percentage of occurrences 20 samples t a = +25c v dd = 2.3 v v dd = 5.5v 120 125 130 135 140 145 150 155 160 -50 -25 0 25 50 75 100 125 ambient temperature (c) cmrr, psrr (db) psrr cmrr v dd = 5.5 v v dd = 2.3 v
? 2011 microchip technology inc. ds25007a-page 9 mcp6v27 note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. figure 2-13: dc open-loop gain vs. ambient temperature. figure 2-14: input bias and offset currents vs. common mode input voltage with t a = +85c. figure 2-15: input bias and offset currents vs. common mode input voltage with t a = +125c. figure 2-16: input bias and offset currents vs. ambient temperature with v dd =+5.5v. figure 2-17: input bias current vs. input voltage (below v ss ). 120 125 130 135 140 145 150 155 160 -50-25 0 255075100125 ambient temperature (c) dc open-loop gain (db) v dd = 5.5v v dd = 2.3v -100 -50 0 50 100 150 200 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input bias, offset currents (pa) i b t a = +85c v dd = 5.5v i os -400 -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input bias, offset currents (pa) i b t a = +125c v dd = 5.5v i os 1 10 100 1,000 10,000 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias, offset currents (a) v dd = 5.5 v -i os i b 1p 10p 100p 1n 10n 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p
mcp6v27 ds25007a-page 10 ? 2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. 2.2 other dc voltages and currents figure 2-18: input common mode voltage headroom (range) vs. ambient temperature. figure 2-19: output voltage headroom vs. output current. figure 2-20: output voltage headroom vs. ambient temperature. figure 2-21: output short circuit current vs. power supply voltage. figure 2-22: supply current vs. power supply voltage. figure 2-23: power on reset trip voltage. -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 -50 -25 0 25 50 75 100 125 ambient temperature (c) input common mode voltage headroom (v) lower (v cml ? v ss ) upper ( v cmh ? v dd ) 1 wafer lo t 10 100 1000 0.1 1 10 output current magnitude (ma) output voltage headroom (mv) v dd ? v oh v dd = 5.5v v dd = 2.3v v ol ? v ss 0 1 2 3 4 5 6 7 8 9 10 -50-25 0 255075100125 ambient temperature (c) output headroom (mv) v dd ? v oh v dd = 5.5 v v ol ? v ss v dd = 2.3v r l = 10 k ? -40 -30 -20 -10 0 10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) output short circuit current (ma) -40c +25c +85c +125c +125c +85c +25c -40c 0 100 200 300 400 500 600 700 800 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) supply current (a/amplifier) +125c +85c +25c -40c 0% 5% 10% 15% 20% 25% 30% 35% 40% 1.25 1.26 1.27 1.28 1.29 1.30 1.31 1.32 1.33 1.34 1.35 por trip voltage (v) percentage of occurrences 820 samples 1 wafer lot t a = +25c
? 2011 microchip technology inc. ds25007a-page 11 mcp6v27 note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. figure 2-24: power on reset voltage vs. ambient temperature. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 ambient temperature (c) por trip voltage (v)
mcp6v27 ds25007a-page 12 ? 2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. 2.3 frequency response figure 2-25: cmrr and psrr vs. frequency. figure 2-26: open-loop gain vs. frequency with v dd =2.3v. figure 2-27: open-loop gain vs. frequency with v dd =5.5v. figure 2-28: gain bandwidth product and phase margin vs. ambient temperature. figure 2-29: gain bandwidth product and phase margin vs. common mode input voltage. figure 2-30: gain bandwidth product and phase margin vs. output voltage. 0 10 20 30 40 50 60 70 80 90 100 110 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) cmrr, psrr (db) cmr r psrr+ psrr- 100 100k 1k 1m 10k -20 -10 0 10 20 30 40 50 60 70 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) open-loop gain (db) -270 -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () | a ol | a ol 1k 10k 100k 1m 10m v dd = 2.3v c l = 60 pf -20 -10 0 10 20 30 40 50 60 70 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) open-loop gain (db) -270 -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () | a ol | a ol 1k 10k 100k 1m 10m v dd = 5.5v c l = 60 pf 100 3.0 h z) 90 2.5 ) u ct (m h v dd = 5.5v gbwp 70 80 15 2.0 a rgin ( prod u 60 70 1.0 1 . 5 h ase m a d width pm v dd = 2.3v 50 0.5 p h in ban d 40 0.0 - 50 - 25 0 25 50 75 100 125 ga 50 25 0 25 50 75 100 125 ambient temperature (c) 120 4.0 h z) 100 110 3.0 3.5 ) u ct (m h 80 90 20 2.5 argin ( h prod u v dd = 5.5v v dd = 2.3v gbwp 70 80 1.5 2 . 0 h ase m n dwidt h 50 60 0.5 1.0 p h a in ba n pm 40 0.0 0 .5 0 .0 0 .5 .0 .5 2 .0 2 .5 3 .0 3 .5 4 .0 4 .5 5 .0 5 .5 6 .0 g a - 0 0 0 1 1 2 2 3 3 4 4 5 5 6 common mode input voltage (v) 120 4.0 h z) 100 110 3.0 3.5 ) u ct (m h 80 90 20 2.5 a rgin ( prod u v dd = 5.5v v dd = 2.3v pm 70 80 1.5 2 . 0 h ase m a d width 50 60 0.5 1.0 p h i n ban d gbwp 40 50 0.0 0.5 00 05 10 15 20 25 30 35 40 45 50 55 ga i 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 output voltage (v)
? 2011 microchip technology inc. ds25007a-page 13 mcp6v27 note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. figure 2-31: closed-loop output impedance vs. frequency with v dd =2.3v. figure 2-32: closed-loop output impedance vs. frequency with v dd =5.5v. figure 2-33: channel-to-channel separation vs. frequency. figure 2-34: maximum output voltage swing vs. frequency. 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) closed-loop output impedance ( ? ) v dd = 2.3 v 100k 1m 10m 100m 1 10 100 1k 10k g = 1 v/v g = 11 v/v g = 101 v/v 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) closed-loop output impedance ( ? ) v dd = 5.5v 100k 1m 10m 100m 1 10 100 1k 10k g = 1 v/v g = 10 v/v g = 100 v/v 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) maximum output voltage swing (v p-p ) v dd = 5.5v v dd = 2.3v 1k 10k 100k 1m
mcp6v27 ds25007a-page 14 ? 2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. 2.4 input noise and distortion figure 2-35: input noise voltage density and integrated input noise voltage vs. frequency. figure 2-36: input noise voltage density vs. input common mode voltage. figure 2-37: inter-modulation distortion vs. frequency with v cm disturbance (see figure 1-6 ). figure 2-38: inter-modulation distortion vs. frequency with v dd disturbance (see figure 1-6 ). figure 2-39: input noise vs. time with 1 hz and 10 hz filters and v dd =2.3v. figure 2-40: input noise vs. time with 1 hz and 10 hz filters and v dd =5.5v. 1,000 10,000 ; o ltage; d ensity ; v dd = 5.5v v dd = 2.3v 100 1,000 o ise v o -p ) l tage d / hz) 10 100 n put n o e ni (v p ise vo l e ni (nv / e ni 10 100 r ated i n e p ut no 1 10 1e 01 1e 02 1e 03 1e 04 1e 05 integ r in p 10 1k 10k 100k e ni (0 hz to f) 100 1 . e + 01 1 . e + 02 1 . e + 03 1 . e + 04 1 . e + 05 fre q uenc y ( hz ) 10 1k 10k 100k 100 0 10 20 30 40 50 60 70 80 90 100 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) v dd = 5.5v v dd = 2.3v input noise voltage density (nv/hz) f < 5 khz 0.1 1 10 100 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) imd spectrum, rti (v pk ) g dm = 1 v/v v cm tone = 50 mv pk , f = 1 khz 100 1k 10k 100k imd tone at dc residual 1 khz tone v dd = 2.3 v v dd = 5.5 v 0.1 1 10 100 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) imd spectrum, rti (v pk ) 100 1k 10k 100k g dm = 1 v/v v dd tone = 50 mv p-p , f = 1 khz imd tone at dc 1 khz tone v dd = 5.5v v dd = 2.3v 0 102030405060708090100 t (s) input noise voltage; e ni (t) (0.2 v/div) v dd = 2.3v npbw = 10 hz npbw = 1 hz 0 102030405060708090100 t (s) input noise voltage; e ni (t) (0.2 v/div) v dd = 5.5 v npbw = 10 hz npbw = 1 hz
? 2011 microchip technology inc. ds25007a-page 15 mcp6v27 note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. 2.5 time response figure 2-41: input offset voltage vs. time with temperature change. figure 2-42: input offset voltage vs. time at power up. figure 2-43: the mcp6v27 device shows no input phase reversal with overdrive. figure 2-44: non-inverting small signal step response. figure 2-45: non-inverting large signal step response. figure 2-46: inverting small signal step response. -14 -12 -10 -8 -6 -4 -2 0 2 4 6 0 20 40 60 80 100 120 140 160 180 time (s) input offset voltage (v) 0 10 20 30 40 50 60 70 80 90 100 pcb temperature (c) t pcb v os temperature increased by using heat gun for 10 seconds. -10 0 10 20 30 40 50 60 70 80 90 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (ms) input offset voltage (v) -4 -3 -2 -1 0 1 2 3 4 5 6 power supply voltage (v) por tri p point v os v dd g = 1 -1 0 1 2 3 4 5 6 7 012345678910 time (ms) input, output voltages (v) v dd = 5.5v g = 1 v out v in 012345678910 time (s) output voltage (10 mv/div) v dd = 5.5v g = 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 time (s) output voltage (v) v dd = 5.5v g = 1 012345678910 time (s) output voltage (10 mv/div) v dd = 5.5v g = -1
mcp6v27 ds25007a-page 16 ? 2011 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.3v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =10k to v l and c l = 60 pf. figure 2-47: inverting large signal step response. figure 2-48: slew rate vs. ambient temperature. figure 2-49: output overdrive recovery vs. time with g = -100 v/v. figure 2-50: output overdrive recovery time vs. inverting gain. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 time (s) output voltage (v) v dd = 5.5v g = -1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -50-25 0 255075100125 ambient temperature (c) slew rate (v/s) falling edge v dd = 5.5v v dd = 2.3v rising edge -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 time (50 s/div) output voltage (v) -1 0 1 2 3 4 5 6 input voltage g (v/v) v dd = 5.5v g = -100 v/v 0.5v overdrive v ou t g v in v ou t g v in 1 10 100 1000 1 10 100 1000 inverting gain magnitude (v/v) overdrive recovery time (s) 0.5v output overdrive t odr , lo w t odr , high v dd = 2.3v v dd = 5.5v
? 2011 microchip technology inc. ds25007a-page 17 mcp6v27 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog outputs the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs (v in +, v in ?, ?) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins the positive power supply (v dd ) is 2.3v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. 3.4 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the v ss pin; they must be connected to the same potential on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ja ). mcp6v27 symbol description dfn msop, soic 11v out , v outa output (op amp a) 22v in ?, v ina ? inverting input (op amp a) 33v in +, v ina + non-inverting input (op amp a) 44 v ss negative power supply 55 v inb + non-inverting input (op amp b) 66 v inb ? inverting input (op amp b) 77 v outb output (op amp b) 88 v dd positive power supply 9 ? ep exposed thermal pad (ep); must be connected to v ss
mcp6v27 ds25007a-page 18 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25007a-page 19 mcp6v27 4.0 applications the mcp6v27 auto-zeroed op amp is manufactured using microchip?s state of the art cmos process. it is designed for low cost, low power and high precision applications. its low supply voltage, low quiescent cur- rent and wide bandwidth makes the mcp6v27 device ideal for battery-powered applications. 4.1 overview of auto-zeroing operation figure 4-1 shows a simplified diagram of the mcp6v27 auto-zeroed op amp. this will be used to explain how the dc voltage errors are reduced in this architecture. figure 4-1: simplified auto-zeroed op amp functional diagram. 4.1.1 building blocks the null amplifier and main amplifier are designed for high gain and accuracy using a differential topology. they have a main input pair (+ and - pins at their top left) used for the signal. they have an auxiliary input pair (+ and - pins at their bottom left) used for correcting the offset voltages. both input pairs are added together internally. the capacitors at the auxiliary inputs (c fw and c h ) hold the corrected values during normal operation. the output buffer is designed to drive external loads at the v out pin. it also produces a single ended output voltage (v ref is an internal reference voltage). all of these switches are make-before-break in order to minimize glitch-induced errors. they are driven by two clock phases ( 1 and 2 ) that select between normal mode and auto-zeroing mode. the clock is derived from an internal r-c oscillator running at a rate of f osc1 = 850 khz. the oscillator?s output is divided down to the desired rate. the internal por ensures the part starts up in a known good state. it also provides protection against power supply brown-out events. the digital control circuitry takes care of all of the housekeeping details of the switching operation. it also takes care of por events. v in + v in ? main output v out v ref amp. buffer nc null amp. null input 1 switches null correct 2 switches null output switches c h c fw por digital control oscillator 1 2
mcp6v27 ds25007a-page 20 ? 2011 microchip technology inc. 4.1.2 auto-zeroing action figure 4-2 shows the connections between amplifiers during the normal mode of operation ( 1 ). the hold capacitor (c h ) corrects the null amplifier?s input offset. since the null amplifier has very high gain, it dominates the signal seen by the main amplifier. this greatly reduces the impact of the main amplifier?s input offset voltage on overall performance. essentially, the null amplifier and main amplifier behave as a regular op amp with very high gain (a ol ) and very low offset voltage (v os ). figure 4-2: normal mode of operation ( 1 ); equivalent amplifier diagram. figure 4-3 shows the connections between amplifiers during the auto-zeroing mode of operation ( 2 ). the signal goes directly through the main amplifier, and the flywheel capacitor (c fw ) maintains a constant correc- tion on the main amplifier?s offset. the null amplifier uses its own high open loop gain to drive the voltage across c h to the point where its input offset voltage is almost zero. because the signal input pair is connected to v in +, the auto-zeroing action corrects the offset at the current common mode input voltage (v cm ) and supply voltage (v dd ). this makes the dc cmrr and psrr very high also. since these corrections happen every 40 s, or so, we also minimize slow errors, including offset drift with temperature ( v os / t a ), 1/f noise, and input offset aging. figure 4-3: auto-zeroing mode of operation ( 2 ); equivalent diagram. 4.1.3 intermodulation distortion (imd) the mcp6v27 op amp will show intermodulation dis- tortion (imd), products when an ac signal is present. the signal and clock can be decomposed into sine wave tones (fourier series components). these tones interact with the auto-zeroing circuitry?s non-linear response to produce imd tones at sum and difference frequencies. imd distortion tones are generated about all of the square wave clock?s harmonics. see figure 2-37 and figure 2-38 . v in + v in ? main output v out v ref amp. buffer nc null amp. c h c fw v in + v in ? main output v out v ref amp. buffer nc null amp. c h c fw
? 2011 microchip technology inc. ds25007a-page 21 mcp6v27 4.2 other functional blocks 4.2.1 rail-to-rail inputs the input stage of the mcp6v27 op amp uses two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm , which is approximately equal to v in + and v in ? in normal operation) and the other at high v cm . with this topology, the input operates with v cm up to v dd +0.2v, and down to v ss ? 0.15v, at +25c (see figure 2-18 ). the input offset voltage (v os ) is measured at v cm =v ss ? 0.15v and v dd + 0.2v to ensure proper operation. the transition between the input stages occurs when v cm v dd ?1.2v (see figure 2-7 and figure 2-8 ). for the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. 4.2.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-43 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 input voltage limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see section 1.1, absolute maximum ratings ? ). this requirement is independent of the cur- rent limits discussed later on. the esd protection on the inputs can be depicted as shown in figure 4-4 . this structure was chosen to protect the input transistors against many (but not all) over-voltage conditions, and to minimize input bias cur- rent (i b ). figure 4-4: simplified analog input esd structures. the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that are well above v dd ; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow over-voltage (beyond v dd ) events. very fast esd events (that meet the spec) are limited so that damage does not occur. in some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; figure 4-5 shows one approach to protecting these inputs. d 1 and d 2 may be small signal silicon diodes, schottky diodes for lower clamping voltages or diode- connected fets for low leakage. figure 4-5: protecting the analog inputs against high voltages. 4.2.1.3 input current limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see section 1.1, absolute maxi- mum ratings ? ). this requirement is independent of the voltage limits previously discussed. figure 4-6 shows one approach to protecting these inputs. the resistors r 1 and r 2 limit the possible cur- rent in or out of the input pins (and into d 1 and d 2 ). the diode currents will dump onto v dd . figure 4-6: protecting the analog inputs against high currents. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 v dd d 1 v out v 2 d 2 u 1 ?mcp6v27 v 1 r 1 v dd d 1 min(r 1 ,r 2 )> v ss ?min(v 1 ,v 2 ) 2ma v out v 2 r 2 d 2 min(r 1 ,r 2 )> max(v 1 ,v 2 )?v dd 2ma u 1 ? mcp6v27
mcp6v27 ds25007a-page 22 ? 2011 microchip technology inc. it is also possible to connect the diodes to the left of resistors r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in ?) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-17 . 4.2.2 rail-to-rail output the output voltage range of the mcp6v27 zero-drift op amp is v dd ? 15 mv (minimum) and v ss +15mv (maximum) when r l =10k is connected to v dd /2 and v dd = 5.5v. refer to figure 2-19 and figure 2-20 . this op amp is designed to drive light loads; use another amplifier to buffer the output from heavy loads. 4.3 application tips 4.3.1 input offset voltage over temperature table 1-1 gives both the linear and quadratic tempera- ture coefficients (tc 1 and tc 2 ) of input offset voltage. the input offset voltage, at any temperature in the specified range, can be calculated as follows: equation 4-1: 4.3.2 dc gain plots figure 2-9 , figure 2-10 and figure 2-11 are histograms of the reciprocals (in units of v/v) of cmrr, psrr and a ol , respectively. they represent the change in input offset voltage (v os ) with a change in common mode input voltage (v cm ), power supply voltage (v dd ) and output voltage (v out ). the 1/a ol histogram is centered near 0 v/v because the measurements are dominated by the op amp?s input noise. the negative values shown represent noise, not unstable behavior. we validate the op amps? stability by making multiple measurements of v os ; an unstable part would show either greater variability in v os , or the output is stuck at one of the rails. 4.3.3 offset at power up when this part powers up, the input offset (v os ) starts at its uncorrected value (usually less than 5 mv). circuits with high dc gain can cause the output to reach one of the two rails. in this case, the time to a valid output is delayed by an output overdrive time (like t odr ), in addition to the startup time (like t str ). it can be simple to avoid this extra startup time. reducing the gain is one method. adding a capacitor across the feedback resistor (r f ) is another method. 4.3.4 source resistances the input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input esd diode leakage currents that dominate at +85c and above. make the resistances seen by the inputs small and equal. this minimizes the output offset caused by the input bias currents. the inputs should see a resistance on the order of 10 to 1 k at high frequencies (i.e., above 1 mhz). this helps minimize the impact of switching glitches, which are very fast, on overall performance. in some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance. 4.3.5 source capacitance the capacitances seen by the two inputs should be small and matched. the internal switches connected to the inputs dump charges on these capacitors; an offset can be created if the capacitances do not match. 4.3.6 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. these auto-zeroed op amps have a different output impedance than most op amps, due to their unique topology. when driving a capacitive load with these op amps, a series resistor at the output (r iso in figure 4-7 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. v os t a () v os tc 1 ttc 2 t 2 ++ = where: t=t a ?25c v os (t a ) = input offset voltage at t a v os = input offset voltage at +25c tc 1 = linear temperature coefficient tc 2 = quadratic temperature coefficient
? 2011 microchip technology inc. ds25007a-page 23 mcp6v27 figure 4-7: output resistor, r iso , stabilizes capacitive loads. figure 4-8 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n 2 ). the y-axis is the normalized resistance (g n r iso ). g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n = +2 v/v). figure 4-8: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso 's value until the response is reasonable. bench evaluation and simulations with the mcp6v27 spice macro model are helpful. 4.3.7 stabilizing output loads this auto-zeroed op amp has an output impedance ( figure 2-31 and figure 2-32 ) that has a double zero when the gain is low. this can cause a large phase shift in feedback networks that have low resistance near the part?s bandwidth. this large phase shift can cause stability problems. figure 4-9 shows that the load on the output is (r l + r iso )||(r f +r g ), where r iso is before the load (like figures 4-7). this load needs to be large enough to maintain stability; it should be at least (2 k )/g n . figure 4-9: output load. 4.3.8 gain peaking figure 4-10 shows an op amp circuit that represents non-inverting amplifiers (v m is a dc voltage and v p is the input) or inverting amplifiers (v p is a dc voltage and v m is the input). the capacitances c n and c g rep- resent the total capacitance at the input pins; they include the op amp?s common mode input capacitance (c cm ), board parasitic capacitance and any capacitor placed in parallel. figure 4-10: amplifier with parasitic capacitance. c g acts in parallel with r g (except for a gain of +1 v/v), which causes an increase in gain at high frequencies. c g also reduces the phase margin of the feedback loop, which becomes less stable. this effect can be reduced by either reducing c g or r f ||r g . c n and r n form a low-pass filter that affects the signal at v p . this filter has a single real pole at 1/(2 r n c n ). the largest value of r f that should be used depends on noise gain (see g n in section 4.3.6, capacitive loads ), c g and the open-loop gain?s phase shift. an approximate limit for r f is: equation 4-2: some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). r iso c l v out ? mcp6v27 1 10 100 1000 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 c l /g n 2 (f) recommended g n r iso () 100p 1n 10n 100n 1 1 10 100 1k g n = 1 g n = 2 g n = 5 g n 10 r g r f v out ?mcp6v27 r l c l r g r f v out ?mcp6v27 c g r n c n v m v p r f 2 k 12 pf c g -------------- - g n 2
mcp6v27 ds25007a-page 24 ? 2011 microchip technology inc. 4.3.9 reducing undesired noise and signals reduce undesired noise and signals with: ? low bandwidth signal filters: - minimizes random analog noise - reduces interfering signals ? good pcb layout techniques: - minimizes crosstalk - minimizes parasitic capacitances and induc- tances that interact with fast switching edges ? good power supply design: - provides isolation from other parts - filters interference on supply line(s) 4.3.10 supply bypassing and filtering with this operational amplifier, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm of the pin for good high-frequency performance. this part also needs a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other low noise, analog parts. in some cases, high-frequency power supply noise (e.g., switched mode power supplies) may cause undue intermodulation distortion, with a dc offset shift; this noise needs to be filtered. adding a resistor into the supply connection can be helpful. this resistors needs to be small enough to prevent a large drop in v dd for the op amp, which would cause a reduced output range and possible load-induced power supply noise. it also needs to be large enough to dissipate little power when v dd is turned on and off quickly. figure 4-11 shows a circuit with resistors in the supply connections. it gives good rejection out to 1 mhz for switched mode power supplies. smaller resistors and capacitors are a better choice for designs where the power supply is not as noisy. figure 4-11: additional supply filtering. 4.3.11 pcb design for dc precision in order to achieve dc precision on the order of 1 v, many physical errors need to be minimized. the design of the printed circuit board (pcb), the wiring and the thermal environment has a strong impact on the precision achieved. a poor pcb design can easily be more than 100 times worse than the mcp6v27 op amp minimum and maximum specifications. 4.3.11.1 pcb layout any time two dissimilar metals are joined together, a temperature dependent voltage appears across the junction (the seebeck or thermo-junction effect). this effect is used in thermocouples to measure tempera- ture. the following are examples of thermo-junctions on a pcb: ? components (resistors, op amps, ?) soldered to a copper pad ? wires mechanically attached to the pcb ? jumpers ? solder joints ?pcb vias typical thermo-junctions have temperature to voltage conversion coefficients of 10 to 100 v/c (sometimes higher). microchip?s an1258 ( ?op amp precision design: pcb layout techniques? ) contains in depth information on pcb layout techniques that minimize thermo-junction effects. it also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. 4.3.11.2 crosstalk dc crosstalk causes offsets that appear as a larger input offset voltage. common causes include: ? common mode noise (remote sensors) ? ground loops (current return paths) ? power supply coupling interference from the mains (usually 50 hz or 60 hz), and other ac sources, can also affect the dc perfor- mance. non-linear distortion can convert these signals to multiple tones, included a dc shift in voltage. when the signal is sampled by an adc, these ac signals can also be aliased to dc, causing an apparent shift in offset. to reduce interference: - keep traces and wires as short as possible - use shielding (e.g., encapsulant) - use ground plane (at least a star ground) - place the input signal source near to the dut - use good pcb layout techniques - use a separate power supply filter (bypass capacitors) for these auto-zeroed op amps v s_ana 50 50 100 f 100 f 0.1 f 1/4w 1/10w to other analog parts ? mcp6v27
? 2011 microchip technology inc. ds25007a-page 25 mcp6v27 4.3.11.3 miscellaneous effects keep the resistances seen by the input pins as small and as near to equal as possible to minimize bias current related offsets. make the (trace) capacitances seen by the input pins small and equal. this is helpful in minimizing switching glitch-induced offset voltages. bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the tribo-electric effect). make sure the bending radius is large enough to keep the conductors and insulation in full contact. mechanical stresses can make some capacitor types (such as ceramic) to output small voltages. use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. humidity can cause electro-chemical potential voltages to appear in a circuit. proper pcb cleaning helps, as does the use of encapsulants. 4.4 typical applications 4.4.1 wheatstone bridge many sensors are configured as wheatstone bridges. strain gauges and pressure sensors are two common examples. these signals can be small and the common mode noise large. amplifier designs with high differential gain are desirable. figure 4-12 shows how to interface to a wheatstone bridge with a minimum of components. because the circuit is not symmetric, the adc input is single ended, and there is a minimum of filtering, the cmrr is good enough for moderate common mode noise. figure 4-12: simple design. figure 4-13 shows a higher performance circuit for wheatstone bridges. this circuit is symmetric and has high cmrr. using a differential input to the adc helps with the cmrr. figure 4-13: high performance design. 4.4.2 rtd sensor the ratiometric circuit in figure 4-14 conditions a three wire rtd. it corrects for the sensor?s wiring resistance by subtracting the voltage across the middle r w . the top r 1 does not change the output voltage; it balances the op amp inputs. failure (open) of the rtd is detected by an out-of-range voltage. figure 4-14: rtd sensor. v dd rr rr 100r 0.01c adc v dd 0.2r 0.2r 3k ? mcp6v27 20 k 1f 200 20 k 1f adc v dd 200 200 3k 3k 1f rr rr v dd 10 nf 10 nf 200 ? mcp6v27 ? mcp6v27 r 3 100 nf 10 nf r 2 r 3 100 nf adc v dd 2.49 k 2.49 k 10 nf v dd r w r w r w r t r b r rtd r 1 r 1 1f 100 3k 3k 20 k 20 k 100 k 100 k 2.49 k 2.49 k r 2 2.55 k 2.55 k ? mcp6v27 ? mcp6v27
mcp6v27 ds25007a-page 26 ? 2011 microchip technology inc. the voltages at the input of the adc can be calculated with the following: 4.4.3 thermocouple sensor figure 4-15 shows a simplified diagram of an amplifier and temperature sensor used in a thermocouple application. the type k thermocouple senses the temperature at the hot junction (t hj ), and produces a voltage at v 1 proportional to t hj (in c). the amplifier?s gain is set so that v 4 /t hj is 10 mv/c. v 3 represents the output of a temperature sensor, which produces a voltage proportional to the temperature (in c) at the cold junction (t cj ), and with a 0.50v offset. v 2 is set so that v 4 is 0.50v when t hj ?t cj is 0c. equation 4-3: figure 4-15: thermocouple sensor; simplified circuit. figure 4-16 shows a more complete implementation of this circuit. the dashed red arrow indicates a thermally conductive connection between the thermocouple and the mcp9700a; it needs to be very short and have low thermal resistance. figure 4-16: thermocouple sensor. the mcp9700a senses the temperature at its physical location. it needs to be at the same temperature as the cold junction (t cj ), and produces v 3 ( figure 4-15 ). the mcp1541 produces a 4.10v output, assuming v dd is at 5.0v. this voltage, tied to a resistor ladder of 4.100(r th ) and 1.3224(r th ), would produce a thevenin equivalent of 1.00v and 250(r th ). the 1.3224(r th ) resistor is combined in parallel with the top right r th resistor (in figure 4-15 ), producing the 0.5696(r th ) resistor. v 4 should be converted to digital, then corrected for the thermocouple?s non-linearity. the adc can use the mcp1541 as its voltage reference. alternately, an absolute reference inside a picmicro ? device can be used instead of the mcp1541. 4.4.4 offset voltage correction figure 4-17 shows an mcp6v27 correcting the input offset voltage of another op amp. r 2 and c 2 integrate the offset error seen at the other op amp?s input; the integration needs to be slow enough to be stable (with the feedback provided by r 1 and r 3 ). figure 4-17: offset correction. v dm g rtd v t v b ? () g w v w + = v cm v t v b g rtd 1g w ? + () v w ++ 2 ------------------------------------------------------------------------------ = g rtd 12r 3 r 2 ? ? + = g w g rtd r 3 r 1 ? ? = where: v t = voltage at the top of r rtd v b = voltage at the bottom of r rtd v w = voltage across top and middle r w ?s v cm = adc?s common mode input v dm = adc?s differential mode input v 1 t hj (40 v/c) v 2 = (1.00v) v 3 =t cj (10 mv/c) + (0.50v) v 4 =250v 1 +(v 2 ?v 3 ) (10 mv/c) (t hj ?t cj )+(0.50v) (r th )/250 (r th ) (r th )/250 c (r th ) c v 4 type k 40 v/c (r th ) (r th ) v 1 v 3 (hot junction (cold junction v 2 thermocouple at t hj ) at t cj ) r th = thevenin equivalent resistance ? mcp6v27 (r th )/250 0.5696(r th ) (r th )/250 c (r th ) c v 4 type k (r th ) 4.100(r th ) v 1 mcp9700a v dd mcp1541 v dd 3k r th = thevenin equivalent resistance (e.g., 10 k ) ? mcp6v27 c 2 r 2 r 1 r 3 mcp661 v dd /2 v in v out r 2 ? mcp6v27 r 4 r 5 v dd /2
? 2011 microchip technology inc. ds25007a-page 27 mcp6v27 4.4.5 precision comparator use high gain before a comparator to improve the latter?s performance. do not use mcp6v27 as a comparator by itself; the v os correction circuitry does not operate properly without a feedback loop. figure 4-18: precision comparator. v in r 3 r 2 v dd /2 mcp6541 v out r 5 r 4 r 1 1k ? mcp6v27
mcp6v27 ds25007a-page 28 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25007a-page 29 mcp6v27 5.0 design aids microchip provides the basic design aids needed for the mcp6v27 op amp. 5.1 spice macro model the latest spice macro model for the mcp6v27 op amp is available on the microchip web site at www.microchip.com . this model is intended to be an initial design tool that works well in the op amp?s linear region of operation over the temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filter-lab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design require- ment. available at no cost from the microchip website at www.microchip.com/maps , the maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.4 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demon- stration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their correspond- ing user?s guides and technical information, visit the microchip web site at www.microchip.com/analog tools . some boards that are especially useful are: ? mcp6v01 thermocouple auto-zeroed reference design ? mcp6xxx amplifier evaluation board 1 ? mcp6xxx amplifier evaluation board 2 ? mcp6xxx amplifier evaluation board 3 ? mcp6xxx amplifier evaluation board 4 ? active filter demo board kit ? p/n soic8ev: 8-pin soic/msop/tssop/dip evaluation board ? p/n soic14ev: 14-p in soic/tssop/dip evaluation board 5.5 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. adn003: ?select the right operational amplifier for your filtering circuits? , ds21821 an722: ?operational amplifier topologies and dc specifications? , ds00722 an723: ?operational amplifier ac specifications and applications? , ds00723 an884: ?driving capacitive loads with op amps? , ds00884 an990: ?analog sensor conditioning circuits ? an overview? , ds00990 an1177: ?op amp precision design: dc errors? , ds01177 an1228: ?op amp precision design: random noise? , ds01228 an1258: ?op amp precision design: pcb layout techniques? , ds01258 these application notes and others are listed in the design guide: ?signal chain design guide?, ds21825
mcp6v27 ds25007a-page 30 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25007a-page 31 mcp6v27 6.0 packaging information 6.1 package marking information 8-lead dfn (4x4 mm) example xxxx nnn yyww pin 1 pin 1 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead soic (150 mil) example nnn 6v27 e/md^^ 3 e 1105 256 mcp6v27e sn^^ 1105 3 e 256 8-lead msop example 6v27 e 105256
mcp6v27 ds25007a-page 32 ? 2011 microchip technology inc. 8-lead plastic dual flat, no lead package (md) C 4x4x0.9 mm body [dfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-131e sheet 1 of 2
? 2011 microchip technology inc. ds25007a-page 33 mcp6v27 8-lead plastic dual flat, no lead package (md) C 4x4x0.9 mm body [dfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-131e sheet 2 of 2
mcp6v27 ds25007a-page 34 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds25007a-page 35 mcp6v27 d n e e1 note 1 1 2 e b a a1 a2 c l1 l
mcp6v27 ds25007a-page 36 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds25007a-page 37 mcp6v27 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6v27 ds25007a-page 38 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2011 microchip technology inc. ds25007a-page 39 mcp6v27
mcp6v27 ds25007a-page 40 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25007a-page 41 mcp6v27 appendix a: revision history revision a (march 2011) ? original release of this document.
mcp6v27 ds25007a-page 42 ? 2011 microchip technology inc. appendix b: offset related test screens input offset voltage related specifications in the dc spec table ( ta b l e 1 - 1 ) are based on bench measurements (see section 2.1 ?dc input precision? ). these measurements are much more accurate because: ? more compact circuit ? soldered parts on the pcb (to validate other measurements) ? more time spent averaging (reduces noise) ? better temperature control - reduced temperature gradients - greater accuracy we use production screens to ensure the quality of our outgoing products. these screens are set at wider lim- its to eliminate any fliers; see tab l e b - 1 . table b-1: offset related test screens electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.3v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2 and r l = 10 k to v l (refer to figure 1-4 and figure 1-5 ). parameters sym min max units conditions input offset input offset voltage v os -10 +10 v t a = +25c ( note 1 , note 2 ) input offset voltage drift with temperature (linear temp. co.) tc 1 ??nv/ct a = -40 to +125c ( note 3 ) power supply rejection psrr 115 ? db ( note 1 ) common mode common mode rejection cmrr 106 ? db v dd = 2.3v, v cm = -0.15v to 2.5v ( note 1 ) cmrr 116 ? db v dd = 5.5v, v cm = -0.15v to 5.7v ( note 1 ) open-loop gain dc open-loop gain (large signal) a ol 114 ? db v dd = 2.3v, v out = 0.2v to 2.1v ( note 1 ) a ol 122 ? db v dd = 5.5v, v out = 0.2v to 5.3v ( note 1 ) note 1: due to thermal junctions and other errors in the production environment, these specifications are only screened in production. 2: v os is also sample screened at +125c. 3: tc 1 is not measured in production.
? 2011 microchip technology inc. ds25007a-page 43 mcp6v27 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6v27 dual op amp MCP6V27T dual op amp (tape and reel) temperature range: e = -40c to +125c package: md = plastic dual flat, no-lead (44x0.9 mm), 8-lead ms = plastic micro small outline package, 8-lead sn = plastic soic (150 mil body), 8-lead part no. ?x /xx package temperature range device examples: a) mcp6v27-e/md: extended temperature, 8ld 4x4 dfn package b) MCP6V27T-e/md: tape and reel extended temperature, 8ld 4x4 dfn package c) mcp6v27-e/ms: extended temperature, 8ld msop package d) MCP6V27T-e/ms: tape and reel, extended temperature, 8ld msop package. e) mcp6v27-e/sn: extended temperature, 8ld soic package. f) MCP6V27T-e/sn: tape and reel, extended temperature, 8ld soic package.
mcp6v27 ds25007a-page 44 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds25007a-page 45 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-020-2 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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